Driving of loads by way of an output stage comprising of a bridge circuit is well known in the art. For example, such circuits are used to drive electric loads, such as direct current spindle motors and direct current voice coil motors. Such bridge circuits may be useful when also the direction of the current supplied to the load has to be controlled. For example, a complete collection of articles on this subject can be found in the catalog of SGS-THOMSON MICROELECTRONICS, “Designers' Guide to Power Products”, June 1992 version, in the chapter entitled “DC and Brushless Motors”. 
FIG. 1 shows a bridge circuit 20. The bridge circuit 20 includes two terminals Vcc and GND for receiving a DC power input. The circuit comprises also two terminals OUT1 and OUT2 for providing a power supply signal to a load LOAD, such as a motor. The circuit comprises two control terminals IN1 and IN2 for control inputs.
In the example illustrated, the bridge circuit 20 is based on a full bridge comprising four electronic switches T1, T2, T3 and T4, such as n-channel metal-oxide-semiconductor (MOS) transistors. Specifically, the switches T1 and T3 form a first half-bridge coupled between the power input terminals Vcc and GND, wherein the intermediate point between the switches T1 and T3 is coupled to the output terminal OUT1. Similarly, the switches T2 and T4 form a second half-bridge coupled between the power input terminals Vcc and GND, wherein the intermediate point between the switches T2 and T4 is coupled to the output terminal OUT2.
The control gates of the switches T1-T4 are driven by means of the signals applied to the control terminals IN1 and IN2, whereby only one of the transistors of each half-bridge may be switched on. For example, in the illustrated embodiment, this is achieved by driving the high side switches T1 and T2 directly with the control signals IN1 and IN2, respectively, while the low side switches T3 and T4 are driven with the inverted version of the control signals IN1 and IN2, respectively. For example, the control terminal of the transistor T3 may be coupled to the terminal IN1 through an inverter P1 and the control terminal of the transistor T4 may be coupled to the terminal IN2 through an inverter P2.
Accordingly, when the voltage at the terminal IN1 is high, the transistor T1 is switched on and the transistor T3 is switched off. Conversely, when the voltage at the terminal IN1 is low, the transistor T1 is switched off and the transistor T3 is switched on. The same operation is performed in a corresponding manner also for the switches T2 and T4 based on the voltage at the control terminal IN2.
By applying appropriately control signals to the terminals IN1 and IN2, the power supply signal provided at the output terminal OUT1 and OUT2 may be a voltage signal having a virtually square wave form with a duty cycle such that the average current flowing through the load LOAD coupled to the output OUT1 and OUT2 assumes a desired value.
For example, FIGS. 2a, 2b and 2c show three examples of the signals provided at the output terminals OUT1 and OUT2 and a respective resulting output voltage Vout between the terminals OUT1 and OUT2 and a possible current iout flowing through an inductive load LOAD. Specifically, in FIG. 2a, the signals OUT1 and OUT2 have the same waveform, and accordingly the voltage Vout between the terminals OUT1 and OUT2 corresponds always to 0V and no current is flowing through the load. Conversely, in FIG. 2b, the output signal OUT2 has shorter pulses and accordingly positive voltage pulses are applied to the load LOAD when the signal OUT1 is high and the signal OUT2 is low.
Finally, in FIG. 2c, the output signal OUT1 has shorter pulses and accordingly negative voltage pulses are applied to the load LOAD when the signal OUT1 is low and the signal OUT2 is high. For example, U.S. Pat. No. 6,594,308 to Galbiati et al. discloses a possible approach for obtaining the signals IN1 and IN2. In this approach, the control signals IN1 and IN2 are obtained through a Phase Shift Modulation (PSM). In this case, a control unit is used which generates the control signals IN1 and IN2 as a function of a digital data value VAL.
For example, as shown in FIG. 3, a digital up-and-down or “bidirection” counter may be used. This counter periodically increments a count value CNT from a minimum value Min until a maximum value Max is reached and then decrements the count value CNT again until the minimum value Min is reached. For example, in case an 8 bit counter is used, the value Min may be 0 (i.e. “0x00”) and the value Max may be 255 (i.e. “0xFF”). Accordingly, the count value CNT oscillates around an average count value Avg, with:Avg=(Max−Min)/2.For example, for an 8 bit counter, the average value Avg may be 127.5.
The count value CNT may be compared with the digital value VAL in order to generate the signal IN2. Specifically, in the example illustrated, the signal IN2 is set to high when the counter value CNT is equal or greater than a first threshold value, which corresponds to the value VAL. Accordingly, in case the value VAL corresponds to 128 (“0x80”), a PWM signal with 50% duty cycle is generated.
The signal IN1 has a symmetric behavior with respect to the value Avg. Specifically, in the example illustrated, the signal IN1 is set to high when the counter value CNT is equal or greater than a second threshold value *VAL, which corresponds to:*VAL=Avg−(VAL−Avg)+1=(Max−Min)−VAL+1.
Accordingly, also in this case, a PWM signal with 50% duty cycle is generated for the signal IN1 when the value VAL corresponds to 128, because *VAL=128. For example, in FIG. 3, the exemplary waveform for the signals IN1/OUT1 and IN2/OUT2 for the signal VAL set to 145, i.e. the signal *VAL is 111. Accordingly, such a digital approach provides a very low cost approach for generating the signals IN1 and IN2. However, this approach has some significant disadvantages.
First of all, the frequency fPSM of the signals IN1 and IN2 depends on the clock frequency fclk and the number of bits C used by the counter. For example, for an 8 bit counter and a 48 MHZ clock signal, the frequency fPSM would be:
      f    PSM    =                    48        ⁢                                  ⁢        MHZ                    2                  8          +          1                      =          93.75      ⁢                          ⁢              kHz        .            Accordingly, an increase of the resolution of the counter by 1 bit indeed halves the frequency of the signals IN1 and IN2.
Moreover, a unitary increment of the value VAL, i.e. a unitary decrement of the value *VAL, e.g. from 111 to 110, will increase the turn-on period of the signal IN1/OUT1 by two clock cycles: a first clock cycle B at the raising edge of the signal IN1 and a second clock cycle D at the falling edge of the signal IN1. Moreover, the same applies also to the signal IN2/OUT2. Specifically, a unitary increment of the value VAL, e.g. from 145 to 146 will decrease the turn-on period of the signal IN2 by two clock cycles: a first clock cycle A at the raising edge of the signal IN2 and a second clock cycle C at the falling edge of the signal IN2. Accordingly, a unitary change of the value VAL, indeed, modifies the duration of the pulse in the voltage Vout provided between the terminals OUT1 and OUT2 by four clock cycles.
U.S. Pat. No. 6,594,308 to Galbiati et al. discloses in this context an approach, which permits to improve this resolution by means of three additional bits, while maintain the resolution of the counter. Specifically, these three bits are used to modify the above periods A, B, C and D, at half-clock-cycle resolution (e.g. the value “000” may mean that the periods of the signal IN1 and IN2 remain unchanged and the value “001” may mean that the periods of the signals IN1 and IN2 should be adapted in order to increase the period of the pulse in the voltage Vout by one half-clock-cycles). This variation may be performed, for example, by anticipating the falling edge of the signal IN2 in the period C by a half-clock-cycle.
A similar approach could also be used by merely using two additional bits, which permit to modify the clock cycles A, B, C and D, at clock-cycle resolution. Accordingly, U.S. Pat. No. 6,594,308 to Galbiati et al. provides an approach that may permit virtually increasing the resolution of the digital signal VAL by three bits (e.g. from 8 bit to 11 bit). However, a further resolution increase has still to be obtained by intervening on the resolution of the digital up-and-down counter, with the negative effect on the frequency fPSM, which from a practical point of view should remain above 20 kz, i.e. above the audible band.